1. Field of the Invention
The present invention relates to an information processing apparatus having a plurality of processors employing a virtual storage system for translating a logical address specified in a program into a real address, and more particularly to an address translation system in such a virtual storage system.
2. Description of the Related Art
Large scale and high speed computers are needed more and more in the engineering and scientific field. Advances in semiconductor integration technique is remarkable. With the aid of the recent hardware technique, computers for exclusive use in engineering and scientific computing aiming at a high speed arithmetic operation and having a large capacity of memory are being manufactured.
The computers for exclusive use in engineering and scientific computing of this type are generally constructed of a vector processing unit (vector processor) exclusively conducting vector operations, an operating system for management of all of the computer resources, and a scalar processing unit (scalar processor) conducting those parts of the engineering and scientific computing which cannot be developed into vector instructions.
In case the computers constructed as above for exclusive use in engineering and scientific computing adopt a virtual storage system, the vector and scalar processors mutually and efficiently execute the engineering and scientific computing program in the logical address space. With the advent of large scaled engineering and scientific computing programs, the logical address space has expanded from conventional 16 MB (Mega Byte) to 2 GB (Giga Byte) and the capacity of the real memory is about 256 MB.
The greater part of the engineering and scientific computing program is often occupied by specific data such as matrix data, as different from the conventional program. It can be considered more efficient to process the program with such specific data in a special way (such as with an address translation method). The data area has in general the following features.
(1) The reference/updating of data in the data area is performed in a concentrated manner for a certain period while the whole program is running.
(2) It is also desirable that interruption of processing (such as a page fault) is to be avoided during the reference/updating operation.
It is efficient not to use the data area as an object of paging for transferring data in units of pages between the main storage and the external storage (i.e., page fixation) and to process the data by a so-called swap-in/out system which makes all of the data reside in the main storage when they are requested and makes all of the data expel out into the external storage when they are not requested.
The scalar processor deals with such a program in a way that pages are fixed, and the access to memory is performed through address translation using conventional segment/page tables and translating a logical address, i.e., the address used in programming, into a real address, i.e., the address allocated in the real storage. Although the tables reside in the main storage, it is common that translation pairs of the logical addresses and real addresses are in part stored in a high speed memory (TLB: Translation Look-aside Buffer) in order to ensure high speed addressing. In contrast, it is necessary for the vector processor to be operated at a high speed. Therefore, in performing the address translation it is necessary to have a high speed translation table (TLB) for all of the areas to be accessed. If the vector processor requires the high speed translation table for all of the table entries, it is difficult to realize the processor because of the large capacity even if current semiconductor integration technique is utilized
One of the countermeasures is to load the program in the main storage with the logical addresses and real addresses coinciding with each other and to perform the operation. Although the address translation table for the vector processor is not needed, there arises a problem that the utilization of the main storage becomes degraded. In particular, with the above countermeasure, it is necessary for the program to occupy the contiguous areas in the main storage. However, after repeated feeding and releasing of the program, the unoccupied areas occur in the main storage in a fragmentary way (fragmentation). Although the sum of the fragmentary portions is satisfactory, the portions are not contiguous relative to each other so that it becomes necessary for execution of a job to wait until a certain continuous unoccupied area become available.
A known document relevant to the present invention is for example the Official Gazette of Japanese patent unexamined publication No. 58-97184 which however does not take into consideration to solve the above problems.